low power vlsi design

₹12500-37500 INR

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Dibuat

lebih dari 9 tahun yang lalu

₹12500-37500 INR

Dibayar ketika dikirim

This project deals with new area of evaluation of low power consumption as well as dissipation less power digital logic circuits. With the help of reversible logic circuits, it is possible to minimize the area and power of sequential digital circuits like flip-flops and shift registers in terms of gates, garbage inputs/outputs and processing speed. It is the new findings and initiates the research of complex digital logic circuits for quantum computers and robust robots.

Verilog / VHDL

ID Proyek: 6781057

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12 proposal

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Aktif 9 tahun yang lalu

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Gratis mendaftar dan menawar pekerjaan

12 freelancer menawar dengan rata-rata ₹27.407 INR untuk pekerjaan ini

@loi09dt1

Visit my profile to see my experience on FPGA design or VLSI Implementation. I'm a researcher on VLSI Implementation. Please contact me for details. thanks.

₹30.000 INR dalam 15 hari

5,0

(14 ulasan)

4,4

@shobhitkapoor

Hi I am having 10+ year of design and verification experience , your work sounds challenging to me and really intrested to work in this new technology. please let me know how can we discuss this further ? and what are your expectations. Thanks SK

₹30.000 INR dalam 10 hari

5,0

(5 ulasan)

4,1

@saf818

Hi I have worked on FPGA based designs. Please provide more details and let me know if you need my services. I am currently available for around 25-30 hours per week Best Regards Syfar

₹30.000 INR dalam 10 hari

5,0

(3 ulasan)

2,5

@ElecCirDesign

Hi, I have PhD in microelectronics circuit design with 15+ years experience in research area. I am an expert in low-power/ high speed circuit design and have well background in customizing and designing new building blocks design and simulation. I can help you.

₹13.888 INR dalam 3 hari

5,0

(1 ulasan)

0,0

@jaydeeprangani

My qualification is M.Tech. in VLSI and Embedded System. I have completed projects on low power design like FIR filter, D-FF, adder and multiplier using cadence tool. My thesis is on low power system with title HDL implementation of AM based instruction predictor for power reduction. I am ready to start working on your job.

₹33.333 INR dalam 15 hari

0,0

(0 ulasan)

0,0

@SANGITAR

We are a design and developed company based in Nagpur,we are familiar with low power design methodologies, you can expect 100 percent time bound results.

₹27.777 INR dalam 10 hari

0,0

(0 ulasan)

0,0

@bezsilicon

A proposal has not yet been provided

₹27.777 INR dalam 10 hari

0,0

(0 ulasan)

0,0

@pratikpatel17

Having an experience in Physical Design at Einfochips Ltd. company and having a good knowledge of Low power techniques and Digital Design.

₹38.888 INR dalam 20 hari

0,0

(0 ulasan)

0,0

@calibersakthi

we have good experience vlsi design engineer to complete project within time period and we will give support any time to clear doubt on your project.

₹16.666 INR dalam 5 hari

0,0

(0 ulasan)

0,0

@ritzhobby02

The reversible logic can be implemented using Tanner EDA tools. Basic gates will be developed and further integrated to complex modules like ALU and processors

₹22.222 INR dalam 10 hari

0,0

(0 ulasan)

0,0

@sandunrathnayake

I'm a Verification Engineer. I have access to some of Best EDA tools.(Talus,DC compiler,Spyglass) 3 year experience in EDA I am a member of a community where we have experts from different sub domains of VLSI. So I can guarantee no stuck in the middle of the project. 1 golden request to provide sufficient details at the beggining and I can drive the rest of work without your push...

₹27.777 INR dalam 10 hari