6095 - Developers in Xylinx - 30/04/2018 01:42 EDT

$30-250 USD

Berlangsung

Dibuat

sekitar 6 tahun yang lalu

$30-250 USD

Dibayar ketika dikirim

Design and optimization of low power VLSI circuits for Leakage power reduction using Clock Gating with GSA

Electronics

Engineering

Verilog / VHDL

ID Proyek: 16830126

Tentang proyek

7 proposal

Proyek remot

Aktif 6 tahun yang lalu

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Gratis mendaftar dan menawar pekerjaan

7 freelancer menawar dengan rata-rata $185 USD untuk pekerjaan ini

@ahmedmohamed85

A proposal has not yet been provided

$250 USD dalam 1 hari

4,9

(395 ulasan)

7,8

@prakashddit

Expertise in Vivado and Xilinx FPGA

$77 USD dalam 1 hari

4,8

(7 ulasan)

3,6

@arunaupul

A proposal has not yet been provided

$166 USD dalam 5 hari

4,6

(1 ulasan)

2,5

Buat proyek seperti ini

Tentang klien

Delhi and Chennai, India

4,6

Memverifikasi Metode pembayaran

Anggota sejak Feb 19, 2014

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