SRAM FPGA controller in Verilog

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Hi guys, I've done a simple design to test the SRAM of Digilent Cmod A7 FPGA board. This is how it works: Using a terminal through UART, I send the input data and address to the SRAM. Then I send address where to read, and I get back the data previously written. Everything works OK except the controller. I need someone to review my design and fix it.

Electrical Engineering

ID Proyek: 17928067

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@prefectworld

Hi, I'm opeoluwa a solid independent specialist, I am so eager to function as a consultant, I am a diligent employee, inspired by meeting set focuses inside due dates, as it gives me a feeling of achievement. I focus on points of interest and guarantee Hi, Am a solid independent specialist, I am so eager to function as a consultant, I am a diligent employee, inspired by meeting set focuses inside due dates, as it gives me a feeling of achievement. I focus on points of interest and guarantee that my work will fulfill your desires. I likewise begin taking lessons to turned into a Experienced FPGA/Verilog/VHDL Engineer hand, to build up my aptitudes around there. I can state I am a genuine all-around collaborator with the capacity to deal with all parts of business while expanding general profitability with effective work.

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