ddr sdram memory controller

This project was part of my project during masters. It was 11T low power SRAM modelling. This project can be done using verilog . The algorithm or digital design will be coded in verilog and then its testbench will be generated to test its output waveforms as shown in paper and so also the schematic as shown in paper. If possible and you are interested, we can even develope some new concepts from my research. I am a VLSI trainer in CDAC authorised training centre in Odisha. Hope can complete your project in time.

Dear sir I have more than 7 years experience in digital design using fpga, also I am the best fpga programmer at freelancer.com please message me so that we can discuss

A proposal has not yet been provided

Hi, I had around 7.5 years of industrial experience in the field of FPGAs and Embedded Systems. I had worked on DDR2 and DDR3 controllers. I can do this project for you. Kind Regards, -- Kamran Babar

Hello. My name is Milos Sapic and I am a Electronics engineer with experience in Digital desigen, i have experience with : Xilinx ISE, Active-HDL, Quartus II 13.0, Nios II 13.0, Qsys you can see in my portfolio. Please choose me and you will not regret and you will be satisfied with the speed and quality of work. I look forward to possible cooperation. Best regards Milos

If this is a sdram memory controller,project budget and avg bid is very less. It involves lots of efforts. Please let me know whether you need the whole RTL or verification environment?

A proposal has not yet been provided