SystemVerilog - Sha1 Algorithm implementation

must know how to code in SystemVerilog

Using Quartus, and ModelSIM

Setting for Quartus:

Family: Arria II GX

Device: EP2AGX45DF29I5

I already have started this and need help completing it

Check PDF 6 (attached file) for more instructions.

It is the project 4.

Look through other PDFs to get a clearer idea of what can and cannot be done.

use the "hints" provided in pdfs 7,8,and9

sha1 needs to work for both test benches I provide

the project 3 described is also part of project 4, which I have already finished. please use everything all the files I have attached.

I have attached my progress on the sha1 module.

will answer and question you have

Also need to be done ASAP (within 12 hours or less)

Verilog / VHDL

ID Proyek: #13973933

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