Verilog / VHDL Jobs

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Tentang Verilog / VHDL
Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Rekrut Verilog / VHDL Designers

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    13 pekerjaan ditemukan, seharga USD
    Make RTL changes in the code to suppor a new Feature -- Project for RaulBehl 6 Hari left
    TERVERIFIKASI

    Have some code which needs updating.

    Verilog / VHDL
    $83 (Avg Bid)
    $83 Rata-rata
    3 penawaran
    Tawar sekarang
    DNB- Vibration monitoring application FFT 6 Hari left

    Need some one who have experience in development for vibration monitoring application along with FFT from scratch.

    Teknik Elektro Elektronika Teknik Matlab and Mathematica Verilog / VHDL
    $2689 (Avg Bid)
    $2689 Rata-rata
    3 penawaran
    Tawar sekarang
    Locking into clock (verilog module) 6 Hari left
    TERVERIFIKASI

    I have a verilog model for digital data and clock recovery using DLL, the code needs debugging, so it needs someone who has a good background in this domain!

    Desain Sirkuit Teknik Elektro Elektronika FPGA Verilog / VHDL
    $25 (Avg Bid)
    $25 Rata-rata
    2 penawaran
    Tawar sekarang
    Convert Verilog to System verilog and add UVM 5 Hari left

    I have working verilog modules, need to convert to system verilog module and add UVM for test bench

    Verilog / VHDL
    $146 (Avg Bid)
    $146 Rata-rata
    4 penawaran
    Tawar sekarang
    Verilog HDL 4 Hari left

    building a simple hardware description of a sequential circuit in Verilog HDL which goal is to produce clock signals for serial communication baud rate generators.

    Teknik Elektro Teknik FPGA Microcontroller Verilog / VHDL
    $85 (Avg Bid)
    $85 Rata-rata
    14 penawaran
    Tawar sekarang
    Working with IDELAYE3 primitives of Xilinx UltraScale FPGA: delay calucaulations 3 Hari left

    Need to implement different logics using primitives like IDELAYE3 / ODELAYE3 primitives to calculate delays accurately with few PS resolution.

    Desain Digital Elektronika FPGA Simulation Verilog / VHDL
    $296 (Avg Bid)
    $296 Rata-rata
    5 penawaran
    Tawar sekarang
    To Read accelerometer from Xilinx FPGA 3 Hari left
    TERVERIFIKASI

    Hello, I have an accelerometer (I2C) and I want to read it and print the output on the terminal through UART. The code must be written in Verilog or SystemVerilog targeting Xilinx FPGAs. It will be tested in a Digilent Cmod A7. Design: I2C Master <-> FSM <-> UART

    FPGA Verilog / VHDL
    $174 (Avg Bid)
    $174 Rata-rata
    4 penawaran
    Tawar sekarang
    8 point DIT FFT algorithm using verilog 3 Hari left

    [login untuk melihat URL] and research paper Explanation [login untuk melihat URL] and PPT

    Teknik Elektro Teknik FPGA Matlab and Mathematica Verilog / VHDL
    $146 (Avg Bid)
    $146 Rata-rata
    2 penawaran
    Tawar sekarang
    FPGA bitstream for kawpow algorithm -- 2 2 Hari left
    TERVERIFIKASI

    I need someone who can Implement optimized bitsteam for both card types cvp13 as well as bcu1525 .As well as DNA locked pc [login untuk melihat URL] file. It should be a Bitsteam and miner application for both cvp13 and bcu1525. Kawpow algorithm minimum hashrate of 400mh for bcu and 650 for cvp I pay you 250 € after successful test From my experience guys are taking a pc miner version that...

    FPGA FPGA Coding Verilog / VHDL
    $231 (Avg Bid)
    $231 Rata-rata
    2 penawaran
    Tawar sekarang
    Helping in desiging a digital Delay locked loop 1 hari left
    TERVERIFIKASI

    I have a verilog model for DLL and the model needs to modify it based on some requirements. This is simple task for the one who has a good background in this context but you will get benifit from continuing with me in this project

    Desain Sirkuit Teknik Elektro FPGA Teknik Telekomunikasi Verilog / VHDL
    $17 (Avg Bid)
    $17 Rata-rata
    4 penawaran
    Tawar sekarang
    Networking Simulation Project Expert 1 hari left
    TERVERIFIKASI

    - Comparing and analysis the performance of existing protocols such as Epidemic, Spray and Wait and PROPHET using ONE Simulator - Required to design and create new routing protocol based on existing protocols such as Epidemic, Spray and Wait and PROPHET protocols using ONE Simulator. - Implement and simulate the new routing protocol using ONE Simulator

    Cisco Java Administrasi Jaringan Verilog / VHDL Nirkabel
    $176 (Avg Bid)
    $176 Rata-rata
    3 penawaran
    Tawar sekarang
    Vitis AI Coach 1 hari left
    TERVERIFIKASI

    Searching for someone with experience in Vitis AI and various HLS optimization techniques. Please leave your hourly rate and experience with Vitis AI. Memory access and computation optimization.

    Linux Machine Learning (ML) Perancangan Perangkat Lunak Verilog / VHDL
    $32 / hr (Avg Bid)
    $32 / hr Rata-rata
    9 penawaran
    Tawar sekarang
    build FPGA to mine bitcoin or other type of crypto currencies 2 jam left
    TERVERIFIKASI

    Anyone interest in building FPGA to mine bitcoin or other type of crypto currencies.

    Pemrograman C Teknik Elektro Elektronika Microcontroller Verilog / VHDL
    $546 (Avg Bid)
    $546 Rata-rata
    5 penawaran
    Tawar sekarang
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