Gambar profil vlsirajagopal
@vlsirajagopal
Bendera India Pudhukottai, India
Anggota sejak 25 September 2013
0 Rekomendasi

vlsirajagopal

Online Offline
Verilog , VHDL, System verilog, UVM. Synopsys VCS, VIVADO,MODELSIM,XILINX ISE, Design vision (Design compiler) , Prime time,TMAX Would like to work on my skills.
$10 USD/hr
15 ulasan
5.0
  • 100%Pekerjaan Diselesaikan
  • 88%Sesuai Anggaran
  • 81%Tepat Waktu
  • 18%Tingkat Rekrut Ulang

Portofolio

Ulasan Terbaru

Pengalaman

Senior verification engineer

Jul 2016 - Nov 2017 (1 year)

Block level verification of ethernet switches.

Verification engineer

Jul 2013 - Jun 2016 (2 years)

Verification of ethernet switch(both custumer end switch, ISP switch) ,Central memory management controller using Systemverilog,UVM.

Asic Design/verification engineer

Jun 2011 - Jun 2013 (2 years)

Verification of ethernet switch ,scheduler,Txole, DMA (AXI) using System verilog UVM.

Pendidikan

BE

2007 - 2011 (4 years)

Kualifikasi

Diploma in ASIC (2011)

RV -VLSI design centre

Whole flow of ASIC with hands on project(Design,DV,STA,PD,Layout).

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