Rajneesh S.

1. 4+ Years of Experience in ASIC/FPGA Design and Verification using Verilog, VHDL. 2. Good experience in HDL/HVL such as VHDL, Verilog and SystemVerilog. 3. Actively involved in RAM (SRAM) development from designing HDL code to successful Tape-out. 4. Expertise in Design/Verification tools Mentor ModelSim, QuestaSim, Cadence IUS and Synopsys VCS. 5. [login to view URL] (VLSI) from Jaypee Institute of Information Technology, NOIDA. 6. Exposure of Lint, Gate Level Simulation (GLS), Clock Domain Crossing (CDC), Functional Equivalence Check (Formality). 7. Good knowledge of Digital concepts, basic electronics, memory. 8. Motivated team player with excellent interpersonal communication skills.