Pavel M. Profile

5,0

(2 ulasan)

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$20 USD / jam

tallinn,

estonia

$20 USD / jam

Saat ini 1:52 PM di sini

Bergabung Juni 12, 2020

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Pavel M.

@botnursery

5,0

(2 ulasan)

1,6

100%

$20 USD / jam

tallinn,

estonia

$20 USD / jam

100%

Pekerjaan Selesai

100%

Sesuai Anggaran

100%

Tepat Waktu

N/A

Tingkat Rekrut Ulang

FinTech & FPGA design

fpga design, digital electronics, low-level programming, radio electronic devices and systems, financial and cryptographic applications

Lihat semua Electronics Engineers in Estonia

Hubungi Pavel M. mengenai pekerjaan Anda

Portofolio

ZYNQ-7000 EBAZ4205 Minimum Board Operating Configuration
EBAZ4205 is mining board used in Ebang Ebit E9+ bitcoin miner machine. This board features 256MB DDR3 memory, 128MB NAND Flash memory, 10/100MBit Ethernet and speed grade -1 Zynq 7010
** New additions and changes in this fork:
https://github.com/botnursery/EBAZ4205-Minimum-Board-Operating-Configuration

ZYNQ EBAZ4205 Base Configuration Design Project

6641105

Datasheet on SHA256 hash checker IP (intellectual property virtual component)
including verilog sourses https://github.com/botnursery/METRICSgit
SHA256 hash checker can be used for massive hash reconciliation or in Bitcoin miners designs.

Datasheet on Verilog SHA256 hasher IP core

FSM (finit state machine) in Verilog to control the taillights of a 1965 Ford Thunderbird modeling

Finit State Machine to control Ford Thunderbir taillights

NIOS II system with SDRAM mapped to VGA

Low level coded (on asembler) module for AVR ATmega328P. ADC to pulse-position modulation (PPM) XY chanels encoder.

PPM (Pulse-position modulation) module

AES circuit and their testbench.
Rijndael substitution box are implemented on forward s-box.
The key length is 128 bits.
https://github.com/botnursery/METRICSgit based on https://github.com/pnvamshi/Hardware-Implementation-of-AES-Verilog

Using the AES encryption module in Xilinx Vivado

ZYNQ EBAZ4205 Base Configuration Design Project

6641105

Datasheet on Verilog SHA256 hasher IP core

Finit State Machine to control Ford Thunderbir taillights

NIOS II system with SDRAM mapped to VGA

PPM (Pulse-position modulation) module

Using the AES encryption module in Xilinx Vivado

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5,0

€30,00 EUR

Quartus Prime (FPGA Intel) Programming Expertise

Pavel was stellar. I have worked with a lot of excellent freelancers in my time but Pavel was constantly going above and beyond to deliver on the project. Without his help the project would have suffered, and instead, with the results he procured the project has really delivered. I cannot emphasize enough what an excellent help Pavel was. Timely, accurate, responsive, on-budget and ultimately more than eager to actually help!

Electronics

Verilog / VHDL

Microcontroller

Electrical Engineering

FPGA

Luis L.

@luislopez1994

•

3 tahun yang lalu

5,0

$30,00 USD

Find FPGA expert - pin assignment

Thanks Pavel. I will contact you again on next job

Electronics

Verilog / VHDL

Microcontroller

Electrical Engineering

FPGA

Closed User

@bwtxzj

•

4 tahun yang lalu

Pengalaman

METRICS Directions OU

Nov 2011 - Sekarang

Startup working group in development and implementation (FinTech). Development of hardware (FPGA) miner, adaptation of the SHA256 hashing for RTL layout in Verilog, analysis of time constraints and clock frequency, preparation of a testbenches. Design and development of DeFi smart contracts (Solidity). Deploying lightning network nodes (LND/LNbits), inspect and maintain functionality. Algorithm development and implementation.