Authored modules on CPAN. Refer: http://search.cpan.org/~jvs/ SVG-Timeline-Compact Verilog-VCD-Writer Submitted bug reports/testcases/patches to various projects. Check https://github.com/jahagirdar/
Major Skill sets are. * Architecture analysis and Digital design (Verilog/ASIC/FPGA) * RTL coding, Verification, Validation and Synthesis. * Languages: Verilog, Tcl, Perl * Domain Expertise: * Cryptography * Wireless Lan * Ethernet (1G/10G/20G/40G/100G) * Display Technology * High Speed Serdes based Protocols. Dyumnin Techonologies is a company founded by me in 2016 with a focus on ASIC/FPGA Design services, EDA Tool development and IP Development. Google website for details.