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$50 USD / hour
Bendera INDIA
bangalore, india
$50 USD / hour
Saat ini 2:42 PM di sini
Bergabung Juni 23, 2017
0 Rekomendasi

Vijayvithal J.

@Dyumnin

4,9 (5 ulasan)
4,6
4,6
100%
100%
$50 USD / hour
Bendera INDIA
bangalore, india
$50 USD / hour
100%
Pekerjaan Selesai
100%
Sesuai Anggaran
100%
Tepat Waktu
25%
Tingkat Rekrut Ulang

20 man years exp in multi-million gate ASIC Design

Major Skill sets are. * Architecture analysis and Digital design (Verilog/ASIC/FPGA) * RTL coding, Verification, Validation and Synthesis. * Languages: Verilog, Tcl, Perl * # Domains: =============== 1. Communication (PCIe, Ethernet, PCS, MAC, Serdes, WLAN ), 2. Cryptography, 3. Video & Display Technologies 4. DSP, 5. SoC and subsystem development Keywords: Verilog, ASIC, FPGA, Synopsys, Xilinx, Altera, Intel, Vivado, Quartus, Modelsim, VCS, Synthesis, Perl, Tcl. ARM, RISC-V, VHDL, BSV, cocotb # Work Experience: ================== Technologies worked on: 1. Networking and communication: Ethernet Subsystems, Wireless LAN, DOCSIS, DTV. 2. Cryptography, 3. Display Subsystem, Video Processing 4. Microcontrollers & Peripherals 5. ARM and RISCV based subsystem design Verilog/VHDL/SystemC/SystemVerilog, Perl, Tcl, Python(cocotb, myHDL). Tapeout's: Contributed to the tapeout of over a dozen ASIC's Why Hire Me? ============== If you ideal candidate is someone who can take your Idea for an IP/Chip and independently or with minimal day to day supervision, drive the entire process from 1. Studying the Product Requirements/Industry Standards. 2. Creating and proposing a suitable Architecture and work plan. 3. Defining the Micro-architecture and driving Verification 4. Implementing and verifying the design. 5. Validating the design. Then I am the right candidate for you. My successful contracts are a mix of 1. Clients expecting and End to End(Steps 1-5 above) Design delivery. OR 2. Clients expecting 1-5 from me and also requiring me to supervise and guide their junior staff for 4 & 5. Employment Details. ([login to view URL]) ================ 1. Texas Instruments: (10 Years) RTL Lead. 2. Intel(6 Years) Architect Ethernet Subsystems. 3. Dyumnin Techologies/Dyumnin Semiconductor (3 years) Co-Founder, Engineer. 3.1. IP Design( Networking, Gaming systems, Cryptography) 3.2. Design automation related tools and products. 3.3. IP Portfolio, Design tools, Design consultation & RTL to Gates services for complex designs.

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Portofolio

3857593
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3857593
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Ulasan

Perubahan tersimpan
Menampilkan 1 - 5 dari 5 ulasan
Filter ulasan menurut:
4,8
$883,70 USD
very professional.
Perl
Verilog / VHDL
R Programming Language
FPGA
+1 lagi
J
Bendera John S.
@johnschugart19
5 tahun yang lalu
5,0
$50,00 USD
Problem solver & very thoughtful looking forward to working with him again
Perl
Verilog / VHDL
R Programming Language
FPGA
+1 lagi
Avatar Pengguna
Bendera Nelson J.
@muzondwa
6 tahun yang lalu
5,0
$1.056,54 USD
Vijay showed he was very knowledgeable in HDL languages and the chips we were working with, Altera and Xilinx. He made himself available as much as he possibly could. Happy with his work and helpful 'lets try this' attitude/ Would work with again.
D
Bendera Alex H.
@datapower
6 tahun yang lalu
5,0
₹458,15 INR
subject knowledge is thorough..very good communication skills..sincere and prompt..
Perl
R Programming Language
FPGA
Scripting
+1 lagi
S
Bendera Shweta A.
@shwetakagliwal
6 tahun yang lalu
5,0
₹1.500,00 INR
Extremely cooperative, knowledge of the subject matter is up to the mark, very good communication skills, patient and courteous. I would definitely hire again
Perl
S
Bendera Shweta A.
@shwetakagliwal
7 tahun yang lalu

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