Designing Simple CPU in verilog

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hi i am an electrical engineer. i have vast experience related to digital circuit design. i have done many digital system projects. i have experience regarding xilinx. let me know if you are interested. we can discuss further on chat.

I am working as FPGA design engineer since last 6 years and I have expertise in both verilog and VHDL. The project which you want to get done, I have complete idea of how they work and I have base work ready for it so I can deliver it in quickest time.

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Below is the project i have done, 16 bit Risc processor in verilog. Feel free to contact me for the code with project report. for(i=0;i<=2;i=i+1) begin PipelineStates [i] = Idle ; InstructionQueue[i] = 8'b00010101 ;//NOP instruction end end end end end endmodule /*------------------------------------------------------------------------*/ /* Program for Microprocessor */ module RiscProcessor(input Clock,input Reset,input [15:0]IN,output Halted,output [15:0]OUT ); wire PCload,MemMux,ReadWrite,Aload,AddSubMux,Rload,OutEnable,OrAndSel,AddSubSel,PCMux,MemEnable, CarryFlag,ZeroFlag ; wire [2:0] Amux ; wire [15:0] Instruction ; wire [7:0] Address ; DataPath DP( Clock,Reset,IN,PCload,MemMux,ReadWrite,Amux,Aload,AddSubMux,Rload,OutEnable,OrAndSel,

Dear Sir/Madam, I’m write this letter to apply for the vacant at your project I have learned in HCM university of technology, I am an logic design engineer. I am working in Arrive Technologies Viet Nam two years. Through my courses at university and my company, I able to work on digital ASIC, FPGA design, knowledge of network and data communication (Carrier ethernet)....Therefore, I think I can fit in this project

I've done a very similar project like yours (except that the number of supported instructions is more) in my Verilog design graduate class. Some clarifications need to be answered but basically, i can do it.

1) defining instruction set architecture 2) Micro architecture design and coding 3) testing for sub modules and confirming functionality 4) integrating and final testing.

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