Verilog projectsPekerjaan

Filter

Pencarian saya terakhir
Filter menurut:
Anggaran
hingga
hingga
hingga
Keahlian
Bahasa
    Pernyataan Pekerjaan
    1,361 verilog projects pekerjaan ditemukan, seharga USD
    200418_Verilog Berakhir left
    TERVERIFIKASI

    All code is written/run on the Quartus Prime version 16 environment =========================================== You have to know Verilog. Please bid only if you know Verilog perfectly Deadline: 72 hours

    $50 - $80
    Bersegel
    $50 - $80
    4 penawaran

    would like to get the implementation of given ieee paper using verilog/vhdl within 15 days

    $388 (Avg Bid)
    $388 Rata-rata
    6 penawaran

    Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's

    $29 (Avg Bid)
    $29 Rata-rata
    11 penawaran

    Tcp sending on FPGA using verilog xgmii xilinx vivado

    $409 (Avg Bid)
    $409 Rata-rata
    4 penawaran

    This is an FPGA/Verilog project to send some TCP packets over 10g SFP+ network to a tcp server.

    $416 (Avg Bid)
    $416 Rata-rata
    5 penawaran
    verilog expert only Berakhir left

    more details will be given in the chat

    $24 (Avg Bid)
    $24 Rata-rata
    15 penawaran

    traffic light controller with priority for emergency vehicles ( Police, Ambulance and firefighters ), I need a state diagram, a working verilog description of the design ( the simulation only) and discussing the results of the simulator (showing the waveform of the simulation)

    $77 (Avg Bid)
    $77 Rata-rata
    1 penawaran
    Mips, Verilog project Berakhir left
    TERVERIFIKASI

    Small project on computer architecture

    $21 (Avg Bid)
    $21 Rata-rata
    20 penawaran

    I need help to clear the error in verilog code to make the fpga work. > Modules are already created with 2 feature of audio effects (delay and musical instrument) >Need help to clear the error, edit the code and make it work in fpga > Only 1 bitstream can be generated

    $13 (Avg Bid)
    $13 Rata-rata
    1 penawaran

    I need the design of a microprocessor with 16 cores and 16 bit data bus with basic MIPS ISA, with 4 stage pipeline. I need the verilog code, testbench and physical design layout and testing (I will provide Synopsys tools)

    $566 (Avg Bid)
    $566 Rata-rata
    12 penawaran

    ...Language=English&CategoryNo=167&No=921) and 2. wiz830mj ([login untuk melihat URL]). The data should be sent to PC by TCP/IP protocol. The correct solution implies Verilog source code, which initializes W5300 chip and sends some data to PC by TCP/IP. The solution should be verified by sending ascending numbers from 0 to 255(8 bits) in an endless

    $111 (Avg Bid)
    $111 Rata-rata
    1 penawaran

    I need Verilog hardware description language expert. I need to modify two modules only: mips.v and mips-control.v. Details are in the attached file.

    $109 (Avg Bid)
    $109 Rata-rata
    7 penawaran

    MIPS and extend in Verilog and datapath for a single-cycle

    $107 (Avg Bid)
    $107 Rata-rata
    4 penawaran
    Verilog HDL Project Berakhir left

    Design a UART module to interface it with a PC

    $88 (Avg Bid)
    $88 Rata-rata
    20 penawaran
    Digital Electronics Berakhir left

    To create a real time audio effects machine using FPGA. It includes the following: 1.Real-time micropho...PmodMIC3 and output at PmodAMP2). 2.Real-time delay in microphone-speaker system. [login untuk melihat URL] Music Instrument. [login untuk melihat URL] integration. [login untuk melihat URL] extra feature (open-ended). Verilog code will be given and it can edit according to th...

    $16 (Avg Bid)
    $16 Rata-rata
    3 penawaran

    I want to generate square wave by using verilog on Altera DE1-SoC and MTL2 with changing the frequency and Duty cycle

    $47 (Avg Bid)
    $47 Rata-rata
    1 penawaran

    Create a real time audio effects machine. provided with a MEMs microphone to capture human voice and an audio amplifier to output your signal through earphones. This manual introduces you to the various concepts involved, and guides (not walks!) you through getting an audio FX machine up and running. Details given below

    $94 (Avg Bid)
    $94 Rata-rata
    8 penawaran

    Write simple Verilog test bench for adder and multiplier.

    $64 (Avg Bid)
    $64 Rata-rata
    26 penawaran
    Digital Alarm clock "verilog " Berakhir left
    TERVERIFIKASI

    I am looking for a freelancer to help me with my project. The skill required is Verilog. Project is to write verilog code for digital alarm clock an will be simulating in Modelsim and will need testbenches as well. message me for more details

    $57 (Avg Bid)
    $57 Rata-rata
    13 penawaran

    Hi This...processor for face recognition. i this project i wrote verilog hdl coding and completed Ai algorithm for face recognition. so the next steps is to do the cross compilation of h.264 verilog coding with AI Algorithm. so iam expecting that to complete cross compilisation of h.264 verilog code with Ai algorithm. regards

    $107 (Avg Bid)
    $107 Rata-rata
    2 penawaran

    I have designed a UART which works fine and I need a testbench to verify it works perfectly.

    $26 (Avg Bid)
    $26 Rata-rata
    13 penawaran

    ...BE/BTECH/ME/MTECH in ECE/EEE. • Work Location : Bangalore / Hyderabad / Pune. Job Description: • Strong in digital design fundamentals. • Hands on experience in Verilog, System Verilog. • Hands on Experience in using any Verification Methodologies like VMM, OVM, UVM. • Desirable experience: Any of Industrial Standard protocols • Hands on experience

    $7667 - $15334
    $7667 - $15334
    0 penawaran

    -This must be done on System Verilog NOT Verilog. -Need to be able to input random data and have results. -Need Explanation for every step taken and code written. (reason why you used the code and math -behind it) -Must have everything Required in the attachment. -Must be able to explain to someone with zero understanding of the topic This

    $155 (Avg Bid)
    $155 Rata-rata
    2 penawaran
    Adder tree Berakhir left

    Parameterizable Verilog module that is calculating sum of N variables. It works in streaming mode and can used in convolution (FIR) and in phased array system.

    $38 / hr (Avg Bid)
    $38 / hr Rata-rata
    1 penawaran

    I need someone expert in ASIC design to design digital clock with VERILOG CODE by Quartus software contact me for more details

    $122 (Avg Bid)
    $122 Rata-rata
    9 penawaran

    Verilog modify processor design to add pipeline, based on MIPS processor. Existing verilog code provided and more details to be provided.

    $79 (Avg Bid)
    $79 Rata-rata
    4 penawaran

    A S type stepper motor controller in verilog. It will take no of steps and frequency as input from ARM MC and generate PWM signal as ouput .

    $199 (Avg Bid)
    $199 Rata-rata
    6 penawaran

    We are developing FPGA using Amazon AWS F1 service. The source code was converted from systemc to verilog using Vivado HLS. Many FPGA tool related issues needs to have an expert to help us. Including: 1) FPGA timing closure constraint 2) Place & route issues. 3) Set up clock divider to CL logic. Potentially, we have a lot more work if you

    $53 / hr (Avg Bid)
    $53 / hr Rata-rata
    5 penawaran

    A stepper motor controller in verilog ,

    $189 (Avg Bid)
    $189 Rata-rata
    15 penawaran

    A S type stepper motor controller in verilog. It will take no of steps and frequency as input from ARM MC and generate PWM signal as ouput .

    $47 (Avg Bid)
    $47 Rata-rata
    1 penawaran

    I need a Stepper motor controller code in verilog, the controller should take Frequency, direction and number of steps as an input and generate a S shape signal for Driver IC , based on that signal the driver IC will control the stepper motor .

    $31 (Avg Bid)
    $31 Rata-rata
    4 penawaran

    ...Buffer input: 1920 x 1080@60 fps, YUV 4:2:2 output: 1920 x 1080@60fps, YUV 4:2:2 • HW Platform DDR3 controller for Xilinx Zynq-7000 or 7-series FPGA • Design output Verilog DDR3 controller source codes, testbench and document...

    $2185 (Avg Bid)
    $2185 Rata-rata
    6 penawaran

    autoamate a door handle using vhdl or verilog

    $102 (Avg Bid)
    $102 Rata-rata
    24 penawaran

    I have some existing code but need to add a serial connection to the hardware. More details to be provided.

    $64 (Avg Bid)
    $64 Rata-rata
    15 penawaran

    Hi, I would like to implement RSA algorithm synthesized code in Verilog up to 512 bit of encryption. - Encryption data output size can vary from 16-bit to 512 bits. - Prime number generation: two random prime number generated through LFSR and should be stored in FIFO - For every iteration different public and private

    $106 (Avg Bid)
    $106 Rata-rata
    9 penawaran

    I need help completing a Single Cycle RISC-V datapath and control using System Verilog. What I need: - A report including how different instructions have be to implemented. The document contains all the necessary modifications in the datapath to add all the instructions. - Modify the code to implement all the instructions.

    $67 (Avg Bid)
    $67 Rata-rata
    6 penawaran

    I'm looking for someone who can write me a verilog HDL code for a servo controller

    $28 (Avg Bid)
    $28 Rata-rata
    7 penawaran

    The project details are in the files: [login untuk melihat URL] or [login untuk melihat URL] Same file different format.

    $31 (Avg Bid)
    $31 Rata-rata
    4 penawaran

    create a digital design that can function as a four-bit full adder or a four-bit subtractor depending on state of switch(on or off)

    $22 (Avg Bid)
    $22 Rata-rata
    7 penawaran

    need a 4-bit carry look ahead adder to be coded in system Verilog using edaplayground. 1) write system Verilog model for CLA 2) parameterize for N bits 3) generate/write test bench that works

    $24 (Avg Bid)
    $24 Rata-rata
    11 penawaran

    We are looking for a FIR filter design in Verilog with the following requirements: - 16-bit input, 16-bit fixed coefficient - 39-bit output - 256 taps Please provide 2 implementations: 1. serial implementation using 1 multiplier 2. partial parallel implementation with 4 multiplers

    $213 (Avg Bid)
    $213 Rata-rata
    5 penawaran

    I need a verilog code for recursive karatsuba multiplier for 16bit signed integers.

    $191 (Avg Bid)
    $191 Rata-rata
    6 penawaran

    ...Proven experience in delivering at least one complex FPGA design project  VHDL, Verilog based RTL design and development  VHDL, Verilog based verification and validation  Familiarity with Xilinx ISE, Vivado Design Suite  Should have worked on ARM SoC based FPGA projects  High Speed Data Acquisition systems  Good knowledge on Timing constraints

    $2228 (Avg Bid)
    $2228 Rata-rata
    3 penawaran

    Hi, since my project deadline is the day after tomorrow want to see is it possible for you to code at least till step 6 of this project.(I attached it also you can see it in my profile) please announce me as soon as possible for you .

    $103 (Avg Bid)
    $103 Rata-rata
    14 penawaran

    Hi, since my project deadline is the day after tomorrow want to see is it possible for you to code at least till step 6 of this project.(I attached it also you can see it in my profile) please announce me as soon as possible for you . thanks

    $139 (Avg Bid)
    $139 Rata-rata
    6 penawaran

    HI, till my project deadline is tomorrow I decided to send it one more time.(I mean who want to do this have to do this in one day). so if you think you can't do whole of the steps just post me that can complete which steps till tomorrow(cause I'll accept that too). project is in file below.

    $33 (Avg Bid)
    $33 Rata-rata
    3 penawaran

    Hi, since my project deadline is the day after tomorrow want to see is it possible for you to code at least till step 6 of this project.(I attached it also you can see it in my profile) please announce me as soon as possible for you .

    $50 (Avg Bid)
    $50 Rata-rata
    1 penawaran

    Hi, since my project deadline is the day after tomorrow want to see is it possible for you to code at least till step 6 of this project.(I attached it also you can see it in my profile) please announce me as soon as possible for you . thanks

    $50 (Avg Bid)
    $50 Rata-rata
    1 penawaran