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    1,880 freelance work fpga design pekerjaan ditemukan, seharga USD
    Design project Berakhir left

    Membuat spectrum analyzer pada fpga de1 menggunakan bahasa vhdl

    $22 - $182
    $22 - $182
    0 penawaran

    Merhaba, bizim bir projede FPGA mühendisine ihtiyacimiz var ve sizinle bu konuda görüsmek istiyorum.

    $10 (Avg Bid)
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    ASIC FPGA Firmware development 4 Hari left
    TERVERIFIKASI

    We are looking for developers/coders specialized in cryptos and blockchain for a project of firmware development. We would like to get a firmware to overclock this mining hardware i.e. graphic cards (GPU) RX580 8Go. Which are the maximum hashrates performances you can get?

    $2056 (Avg Bid)
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    ...and 4K horizantal resolutions. During line scan mode we need to reach 25 kHz. Area scan speed can be any 10-30 fps. We will use OS08A20 CMOS image sensor and Altera or Xlinx FPGA. As the milesotones: 1. Creation of camera controller to achive area scan and high speed line scan functions. 2. Sending image over USB 3.0 or Gigabit ethernet 3. Testing

    $1 / hr (Avg Bid)
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    ...and 4K horizantal resolutions. During line scan mode we need to reach 25 kHz. Area scan speed can be any 10-30 fps. We will use OS08A20 CMOS image sensor and Altera or Xlinx FPGA. As the milesotones: 1. Creation of camera controller to achive area scan and high speed line scan functions. 2. Sending image over USB 3.0 or Gigabit ethernet 3. Testing

    $1 / hr (Avg Bid)
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    1 penawaran

    ...and 4K horizantal resolutions. During line scan mode we need to reach 25 kHz. Area scan speed can be any 10-30 fps. We will use OS08A20 CMOS image sensor and Altera or Xlinx FPGA. As the milesotones: 1. Creation of camera controller to achive area scan and high speed line scan functions. 2. Sending image over USB 3.0 or Gigabit ethernet 3. Testing

    $1 / hr (Avg Bid)
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    Dear Muhammad, I am looking for an Hardware Engineer having experience with FPGA/ASIC in the Ethernet area. We want to build and develop a product and it looks that you would be able to do that. More details about the project I would share in the chat.

    $10 (Avg Bid)
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    ..."MagicNumber(2 bytes), Length(2 bytes), Payload(252 bytes)" 0xAA 0x55 , 0x00 0xFC , rest 252 bytes data 3. Main clock for FPGA is 50MHz. 4. Data read from FIFO is at main clock (50MHz). 5. Clock cross over should be handled without any data lose. 6. Timing contraints should be properly mentioned

    $110 (Avg Bid)
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    more details will be given in the chat only serious expert and my maximum budget for this task is $100

    $56 (Avg Bid)
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    ... ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing

    $1038 (Avg Bid)
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    4 penawaran

    We require a PCB designer familiar with gerber files and PCI Express FPGA designs. We have a reference design and we require the design simplifying so the board only provides the functions required to run our software as effective as possible.

    $232 (Avg Bid)
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    hello, everyone i would like to hire fpga and verilog experts if you have experience on fpga, please bid on my project. thanks.

    $530 (Avg Bid)
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    Essay Writing Berakhir left

    Hardw...artificial neural networks, machine vision and other machine learning algorithms for robotics, internet of things and other data-intensive or sensor-driven tasks. • SW, GPU, FPGA, ASICs, Heterogeneous computing • Examples: • Virtual machines and environments for NN acceleration • Nvidia Volta/Tesla application for NN acceleration Es

    $55 (Avg Bid)
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    The task is to develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with [login untuk melihat URL]; a. The source can

    $625 (Avg Bid)
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    ...looking for someone who can design a FPGA based x16r miner to mine Cuckoo Cycle based coins like rvn. The design should be adaptable for possible changes in the x16r algorithm. Use vivado or other software make bitstream for vu9p fpga card with pcie,like xilinx vcu1525. make a miner software for ubuntu or windows. FPGA should be capable of mining

    $5731 (Avg Bid)
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    find fpga projects Berakhir left

    Hi somebody needed for find fpga (verilog-vhdl) remote projects I paid 20% commission for each project

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    Hi, I need a quick prototype for an Artix-7 based fpga that makes a pcie to sd card controller (SD host controller/SD bus). Objective is to have a fpga card (working on pcie screamer) recognized as a SD/MMC card reader under windows, I need Windows to recognize/be able to install the windows built-in sd card drivers for the card. I don’t need it

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    Arduino that can record signal data and playback the data. it will be inline. I have a FPGA and an LCD. I need to record the signals coming from the FPGA to the LCD and recreate the signal to display on the LCD

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    I would like a board designed in Altium Designer, KiCAD or Eagle that is PIN compatible with the ZYBO Z7-20 board from diligent, but has only the essential circuitry required for RAM, Power, Jtag, and the CSI camera. Please and thank you.

    $15 - $25 / hr
    $15 - $25 / hr
    0 penawaran

    I would like a board designed in Altium Designer, KiCAD or Eagle that is PIN compatible with the ZYBO Z7-20 board from diligent, but has only the essential circuitry required for RAM, Power, Jtag, and the CSI camera. Please and thank you.

    $591 (Avg Bid)
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    GIVE ME SOME IDEAS ABOUT PROJECTS USING FPGA BOARD I need some ideas(NEARLY 10) for my projects by using [login untuk melihat URL] is an electronics and communication engineering project.I need some new ideas. Give me an example idea for accepting the [login untuk melihat URL] should use only fpga and some sensors only.

    $2018 (Avg Bid)
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    hi, everyone i would like to hire fpga and verilog expert if you have experience on fpga, please bid. thanks.

    $520 (Avg Bid)
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    Hello I'm looking for a talented FPGA developer who have rich knowledge of C/C++, Python I have a machine using Huawei's FPGA used vu9p core and I am going to port x13bcd hash algorithm to this machine And I want at least 300mh/s with x13bcd but will increase double using x16R I am using Ubuntu and you can check your project via remote Other details

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    fpga image fusion Berakhir left

    i want you to do project for medical image fusion of CT scan and MRI using xilinix fpga

    $244 (Avg Bid)
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    ... ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing

    $11854 (Avg Bid)
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    ... ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing

    $10386 (Avg Bid)
    $10386 Rata-rata
    1 penawaran

    ... ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing

    $894 - $901
    $894 - $901
    0 penawaran

    ... ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing

    $882 - $882
    $882 - $882
    0 penawaran

    ... ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing

    $884 - $884
    $884 - $884
    0 penawaran

    ... ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing

    $896 (Avg Bid)
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    3 penawaran

    ... ( Dont bid if you are not agree my terms) Hello /////////////////////////////////// ///////////////////////////////// ///////////////////////////// Looking for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing

    $736 - $883
    $736 - $883
    0 penawaran

    I have a 4 layers PCB fully done in Alti...to connect a new EXP main connector to the FPGA. Some nets may be missing in schematics, you should manually add the net names to the schematics. Although the schematic need slight fix, the PCB's DRC is ok, no errror. The EXP connector is DIL 2x12 2.54mm pitch, where signals have to be connected to the FPGA..

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    Hello, I have a set of ECG signal values in numeric form, I want to display them throu...want to display them through Xlinx code and send the same signal to network device through wifi. Please let me know if you can do it in 2 days. The code will not run on actual FPGA board, its just a simulation project. The code should run on xilinx ise software.

    $120 (Avg Bid)
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    FPGA XC6SLX25, Power source 12v. Connect PROM(at least 2 megabyte) and RAM(at least 100kilobyte) to FPGA and power

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    FPGA project Berakhir left

    i need someone to take a FPGA and make it compatible with a MIPI LCD.

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    FPGA load Flash Berakhir left

    loading a Xilinx SPI flash from external serial source using FPGA

    $360 (Avg Bid)
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    ...board from Terasic. I am trying to changing the FPGA code DE10-Nano board to add our H/W interface to it. I have trouble to get the correct starting point for the FPGA that will be used with Linux. If you are expert with this board, please help us to provide support to us. Who am I: I am a FPGA design expert, but know nothing about DE10-Nano. I looking

    $27 / hr (Avg Bid)
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    VHDL FPGA Project Berakhir left

    ...the use of VHDL language to describe a simple design and to verify its correct operation through test benches and simulations. The implementation on a specific FPGA has to allow also to obtain additional information of consumption, frequency of operation, etc. In short, it is a matter of following a design process as close to the real as possible, but

    $741 (Avg Bid)
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    i already have the 90% of the code just need to finish 10% and guide me on running the code my my board

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    8 penawaran

    this is fairly a simple project let make now if you ca do it i will attach files read that the budget is also good $200 and i need it asap

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    8 penawaran

    this is fairly a simple project let make now if you ca do it i will attach files read that the budget is also good $200 and i need it asap

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    ...given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results should be demonstrated on MATLAB by comparing MATLAB result with Xilinx@ System Generator result for above specified 3 images with different

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    VHDL implemented in altera de2 board

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    Our group wants to implement a game using altera de2 cyclone ii board. Please see the attached file for the details of the game to be implemented.

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    Responsibilities: 1. Engaged in ARM embedded software development (zynq7000 platform development); 2. Debugging WiFi driver and USB driver 3. Build and compile the ke... Build and compile the kernel driver environment 4. Realize the interaction between PS and PL 5. Porting algorithms to embedded platforms (including but not limited to ARM, FPGA, etc.)

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    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

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    5 penawaran

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    $179 (Avg Bid)
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    ...deconding and encoding. this will be run on an MyRIO unit so should either be written for this or easily ported from another DAQ system. Ideally it would utilise the RT Module and FPGA Module and operate with as little overhead as possible. The VI should be able the, in terms of the decoder, output a string or timestamp with the current real time LTC timecode

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