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    693 altera quartus pekerjaan ditemukan, seharga USD
    Frame builder 5 Hari left

    Hello , i have an VHDL project it is a frame builder (Quartus II)

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    hi i have an Arria V GX 5AGXFB3H4F35C4N. i want a camera module and the best and easy way u can interface it with my fpga to creat an output as hexadecimal values and i also want pin assignments for the camera in my fpga. i am using quartus

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    2 projects of a Digital Design FPGA Implementation of a Direction Discriminator and Counter for Incremental Encoders You are required to design a 2 fully-digital, hardware-based direction discrimination and counting system for use with quadrature encoder-based rotatory incremental encoders. Your design is to be implemented using an FPGA and verified by both simulation and physical implementatio...

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    Need a Verilog expert with knowledge of ALtera Quartus and pipeining.

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    i need to make game using DE2-115 board and make the hardware design in Quartus and qsys 16.1. i want the code to be implemented in Verilog and show me how to make it work too. i need this in two or three days this is a embalmed system project.

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    1. You have to teach us about RISC-V microcontroller architecture top to bottom and instructions . 2. You have to teach us about VHDL / VERILOG. 3. You can deal it with logisim software. 4. You have to give support and help us to build RISC-V microcontroller in FPGA. 5. You can take class about these minimum 2 days in online. 6. You will get 4 month to complete this. You will get 150$ as p...

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    [login untuk melihat URL] have to teach us about RISC-V microcontroller architecture top to bottom and instructions . [login untuk melihat URL] have to teach us about VHDL / VERILOG. [login untuk melihat URL] can deal it with logisim software. [login untuk melihat URL] have to give support and help us to build RISC-V microcontroller in FPGA. [login untuk melihat URL] can take class about th...

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    Tasks and scheduling Interruptions Race Direct access to peripherals

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    Gostaria de uma alteração no plugin Amelia. É um plugin de booking de atividades. Eu possuo uma clinica com algumas salas. hoje o plugin ja possui cadastro de localização, funcionários e agendamento de horário para o funcionário_x_local. (via calendário) Eu gostaria de criar um cadastro de SALA, para cadastrar o numero de salas que...

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    The project's goal is to have two I2S codecs, both at the same samplerate, selectable 48/96/192KHz, connected to a CPLD and the CPLD to provide a TDM protocol for connection to a MCU. Codecs will have 48/96/192KHz, stereo, 32bits sample depth and will work at I2S protocol. Codecs will perform both capture and playback concurrently. The TDM protocol should have 4 slots for channels. Some po...

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    There is a medium size project for C y c l o n e IV FPGA under Quartus written in VHDL. This complete project needs to be translated in to Verilog language. After conversion project needs to be tested to confirm functionality in Verilog. This is required for university studies thus I will not be able to pay much for this work. Please be realistic with your bids. Thank you.

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    For design on quartus ii digital electronic

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    I have a project to submit pretty soon although we haven't had any real lessons about vhdl yet . We need your help to make us a vhdl program with quartus lite 18.1 that showcase ascii characters, name and phrases scroll on the seven segments of the DE10-LITE fpga and that we can modify on the code to make the word of our choice scroll and we can only use std_logic and std_logic_vector (no int...

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    I need people who understand and professional for Quartus ii

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    Quartus ii Berakhir left

    Quartus program Cacolate

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    Project for Kaif L. Berakhir left

    Enter 8 number in 2' compliment then sorting number 8 number from min to max AND max to min. run this in quartus2 with VHDL or dedicate microprocessor in quartus 2 . Output this project I will send you later if you accept my work.

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    Hi, I need FPGA expert for Altera DE1 Board. I will provide library file, I will share more details in chat. please place bid if you can complete this job. thanks

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    Simplifying a truth table and implementing using gates using Quartus, will provide more details in chat.

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    Assembly using Altera Monitor Program

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    I need to get 4 miliseconds data from AD9226 12bit ADC using ALTERA EP4CE6E22C8 + HY57V561620FTP-H 256Mbit SDRAM when I push a button B1. When I push second time the button B1, to get another 4 ms of data. When I push another button B2, the data from SDRAM must be sent to a CP2102 TTL-USB adapter at 115200 baud rate, so I can donwload data to PC. The aquisition speed needs to be 65MHz.

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    I want long term employee. altera quartus II is needed. its simple project

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    I have no experience using VHDL. I would appreciate if the design and simulation could be explained to me upon creation. I need to create a "Digital Watch" circuit according to specific guidelines so I can implement it on a DE 10-Lite board. I am looking for someone who has experience using VHDL to implement on Intel DE 10-Lite boards. Deliverables Use the slide switches, sw9 to sw4 ...

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    Looking for implementation of exercise in quartus and de Series board. Exercise is about switches, lights and multiplexers alongside latches, flip flops and registers.

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    This Project is to code exercises on latches, flip-flops and registers along with switches, lights and multiplexers VHDL -- Quartus Prime Lite 18.1 Quartus. Altera De-Soc board hardware implementation

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    I need help in doing record for VHDL code and write the observations from the code. Code is working good but need help writing the observations from it. VHDL and De2-115 board

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    I have a board DE0-Nano-S0C. I want to create a dsp system in quartus prime software as mention in diagram

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    Atualmente estou com site de vendas de ingressos gerenciado por fooevents. dentro do wordpress. Esse site ele disponibiliza alguns temas pré prontos e eu quero altera-los. Já tenho o projeto dos emails prontos, só basta passar para codigo fonte. Não precisa "criar codigo" basta apenas pegar do tema atual. tema padrão, [login untuk melihat URL]

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    designe testbench code simulation as a picture give him (the picture give you what can do )on quartus a simulation of the 4 bit counter. This is to include a range of simulated inputs with a suitable explanation of manually derived equivalents that prove the simulation is working, thus validating it. And the standard circuitry is enhanced in some way. For example, converting the 4 bit counter to a...

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    designe (the picture give you what can do )on quartus a simulation of the 4 bit counter. This is to include a range of simulated inputs with a suitable explanation of manually derived equivalents that prove the simulation is working, thus validating it. And the standard circuitry is enhanced in some way. For example, converting the 4 bit counter to a 8 bit counter, or simply including a reset / ...

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    I need some one design and develop tested using Quartus II

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    It is a serial data splitter from 1 input source to 16 output sink using FPGA with specification as below: * synchronous data transfer * simplex data transfer (from source to sink), using TxD, RxD, TxClock , RxClock * there are 2 modes of clock operation which is selectable using gpio pin : external clock source or internal clock source * data buffer for input and all output channel * preferable t...

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    The project here is to write multiple conditions/actions using VHDL format, that can all be displayed in 1 single program. And tested on an Altera DE2 board Port mapping could be okay but using relatively basic principles is ideal. That is (all are not required): Case statements Else / ElseIf Signals Variables Shift register Flip Flops Multiplexer / De-multiplexer Multibit adder A...

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    I need a design implemented that utilizes the Altera Max 10 FPGA (document with pins attatched) as a decoder to have an Analog Potentiometer (A/P) control RGB LEDs (document attached). Ideally the potentiometer would control the brightness of one of the colors and be able to switch between red, green, or blue. This does not need to actually be programmed onto the board. The schematic, code, and te...

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    I need a design to be theoretically implemented that utilizes the Altera Max 10 FPGA (document with pins attatched) as a decoder to have an Analog Potentiometer control RGB LEDs (document attached). In addition, I need a rough description of what your inputs/outputs on your design are doing and how the decoder works. What you will provide (An example of your results is shown) - TOP Level Schemat...

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    Project: The project consists of multiple phases. It is to develop a waveform viewer (WV) that can send data to a PC for display. The data collection is done on the FPGA board. A microprocessor gets data from the FPGA board and sends data to the PC through either a Bluetooth modem or a USB port. The system supports three analog channels, with a single-level triggering. Only 8 bits of precision wil...

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    Project: The project consists of multiple phases. It is to develop a waveform viewer (WV) that can send data to a PC for display. The data collection is done on the FPGA board. A microprocessor gets data from the FPGA board and sends data to the PC through either a Bluetooth modem or a USB port. The system supports three analog channels, with a single-level triggering. Only 8 bits of precision wil...

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    I need help in making a Frogger game in Verilog and need to use 7-sig Altera board

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    I need help in making a Frogger game in Verilog and need to use 7-sig Altera board

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    Design a UART transmitter to serially transmit data from the DE2 board via the serial link to a PC running a terminal program. The PC should then display the ASCII value of the data transmitted.

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    This Project is to investigate latches, flip-flops and registers. VHDL -- Quartus Prime Lite 18.1 Quartus. design simple processor

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    Altera de1 board code changing in C language i already have the solution need a new code based on this one so simple change it for me

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    Create a project about a 128x3 (128 words, with 3 bits at each word) single-port RAM in Verilog, simulate the design, and load it into the Cyclone IV chip on the DE0-Nano board. The design uses two push-buttons and one DIP switch as inputs. •One side of the DIP switch clears the memory address (not the memory contents). •The depressing of the first push-button indicates a memory write...

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    I need a small CPU project prepared, to teach and demonstrate CPU construction. It should be able to fit on an Intel Altera. It should use RISC. The key components are the ability to explain why cache's were chosen, why addressing was chosen, and what options existed. 8-bits. It should be built using blocks, such that I can remove a block, and code in my own block, and assuming all is good, w...

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    PART A Create a project about a 128x3 (128 words, with 3 bits at each word) single- port RAM in Verilog, simulate the design, and load it into the Cyclone IV chip on the DE0-Nano board. The design uses two push-buttons and one DIP switch as inputs. One side of the DIP switch clears the memory address (not the memory contents). The depressing of the first push-button indicates a memory wr...

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    PART A Create a project about a 128x3 (128 words, with 3 bits at each word) single- port RAM in Verilog, simulate the design, and load it into the Cyclone IV chip on the DE0-Nano board. The design uses two push-buttons and one DIP switch as inputs. One side of the DIP switch clears the memory address (not the memory contents). The depressing of the first push-button indicates a memory wr...

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    Create a project about a 128x3 (128 words, with 3 bits at each word) single-port RAM in Verilog, simulate the design, and load it into the Cyclone IV chip on the DE0-Nano board. The design uses two push-buttons and one DIP switch as inputs. •One side of the DIP switch clears the memory address (not the memory contents). •The depressing of the first push-button indicates a memory write...

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    Need an extra eyes to review my Altera design. You must has done a design with Altera Cyclone IV E. If you can show me that you have a design with Cyclone IV E, you are in. What I need from you is to review my Cyclone schematic, it should from 1 to 2 hours total. I had problem with configuration chip with my Cyclone IV E FPGA, need your help.

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    Do you have FPGA board? If yes I have a simple task to be done in FPGA with a sim,ple report. Interested freelancer is expected to use VHDL Language. Quartus V 17.0 will be better. Link will be provided Please bid only if you can work with Quartus and V17.0 to be prpecise. Its needed ASAP

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